Tejeswara Reddy Dudyala

RTL Design Engineer

Specialized in ASIC RTL Design with 2+ years of experience in DVB-S2/S2X protocols, FSM-based design, and verification. Passionate about creating efficient hardware designs and advancing in VLSI technology.

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Professional Experience

RTL Design Engineer

Krisemi Design Technologies, Bengaluru | Jan 2024 - July 2025 (1 Year 7 Months)
  • Worked on RTL Upgrade of 3 modules from DVB-S2 to DVB-S2X version
  • Written FSM-based RTL for the modules present in the DVB-S2 protocol
  • Developed comprehensive understanding of each module in DVB-S2
  • Verified each module of DVB-S2 & DVB-S2X in Vivado Simulation

Design Verification Trainee

Moschip Institute of Silicon Systems, Hyderabad | June 2023 - December 2023 (7 Months)
  • Designed 16-bit ALU and 8-bit Customized up-down counter using Verilog
  • Performed Verification using SystemVerilog
  • Worked on Verification of APB based 10/100 ETHERNET and AMBA-3 APB Protocol
  • Built UVM Verification architecture from scratch to functional coverage and ABV

Technical Skills

Hardware Design

HDL: Verilog
HDVL: SystemVerilog
Concepts: FSM Based Designing, Lint, CDC, Clock Gating, ASIC Flow

Protocols

Worked On: AMBA APB3, 10/100 APB Based ETHERNET, DVB-S2, DVB-S2X
Known: AXI4, SPI, DMA, FIFO

Tools & Environment

EDA Tools: Questasim, Vivado
Scripting: Python with LLMs
Version Control: Github
OS: Linux (Ubuntu 20, 24), Windows

Architectures

Known: Basics of CISC, RISC (MIPS)
Focus: Digital design optimization and hardware-software interface

Key Projects

DVB-S2 and S2X IP Development

ODC Project | Jan 2024 - July 2025 (1Y 7M)
  • Designed Mode Adaptation Module using FSM-based design
  • Designed CRC8 calculator for 8-bit input
  • Upgraded 3 modules (Frame_length_enforcer, LDPC, PL) from DVB-S2 to DVB-S2X
  • Module by Module Verification on Vivado
  • Complete System Verification of DVB-S2 and DVB-S2X

APB Based ETHERNET Protocol

Internal Project | Oct 2023 - Dec 2023 (3 Months)
  • Analyzed Ethernet architecture and functionality
  • Prepared comprehensive Verification, Test, Coverage and Assertion plans
  • Implemented IP level verification using UVM environment
  • Conducted Code and Functional coverage analysis
  • Performed assertion-based formal verification

AMBA 3 APB Protocol

Internal Project | Sept 2023 - Oct 2023 (1 Month)
  • Studied APB protocol specifications in detail
  • Developed Verification, Test, Coverage and Assertion plans
  • Implemented protocol verification in SV and UVM environments
  • Created Functional coverage model and Assertions

UP-DOWN COUNTER & ALU Design

Internal Projects | July 2023 - Sept 2023
  • Designed and implemented 8-bit Up-Down Counter
  • Developed 16-bit ALU design
  • Verified designs in SystemVerilog environment
  • Implemented Coverage and Assertions for functional verification

BLDC Motor Control Analysis

Academic Project
  • Analyzed speed control of BLDC motor using different control techniques
  • Simulation and analysis performed in MATLAB
  • Comparative study of various control algorithms

Home Automation System

Academic Project
  • Designed low-cost home automation circuit
  • Implemented IR remote-based switching control
  • Used microcontrollers and relays for appliance control

Education

Master of Technology (M.Tech)

Birla Institute of Science and Technology, Pilani - Online
Work Integrated Learning Program | Jan 2025 - Dec 2026
Specialization: VLSI Design & Microelectronics (Ongoing)

Bachelor of Technology (B.Tech)

R V R & J C College of Engineering, Guntur, AP
Full Time | Aug 2019 - April 2023
Electrical and Electronics Engineering | CGPA: 9.13

Get In Touch

Feel free to reach out for collaborations, opportunities, or just to connect!

Email dtejaswarreddy10@gmail.com
Phone +91 9110727080
LinkedIn View Profile
Location Kadapa, India